Tuesday, June 11, 2002, 10:30 AM - 12:00 PM | Room: 288

SESSION 3
  Design Innovations for Embedded Processors
  Chair: Vojin Zivojnovic - Axys Design Automation, Inc., Irvine, CA
  Organizers: Grant E Martin, Majid Sarrafzadeh

  This session presents a number of interesting innovations in design techniques for embedded processors. The first paper reveals a novel technique for mixing compiled-code and interpreted-code approaches to instruction-set simulation. The second paper introduces the idea of incorporating optimized hardware for profiling memory. The final paper reduces instruction memory size using decompression hardware.

    3.1
A Universal Technique for Fast and Flexible Instruction-Set Architecture Simulation

  Speaker(s): Achim Nohl - Aachen Univ. of Tech., Aachen, Germany
  Author(s): Achim Nohl - Aachen Univ. of Tech., Aachen, Germany
Gunnar Braun - Aachen Univ. of Tech., Aachen, Germany
Andreas Hoffmann - Aachen Univ. of Tech., Aachen, Germany
Oliver Schliebusch - Aachen Univ. of Tech., Aachen, Germany
Heinrich Meyr - Aachen Univ. of Tech., Aachen, Germany
Rainer Leupers - Aachen Univ. of Tech., Aachen, Germany
    3.2
A Fast On-Chip Profiler Memory
  Speaker(s): Roman Lysecky - Univ. of California, Riverside, CA
  Author(s): Roman Lysecky - Univ. of California, Riverside, CA
Susan Cotterell - Univ. of California, Riverside, CA
Frank Vahid - Univ. of California, Riverside, CA
    3.3
Design of an One-Cycle Decompression Hardware for Performance Increase in Embedded Systems
  Speaker(s): Haris Lekatsas - NEC, Princeton, NJ
  Author(s): Haris Lekatsas - NEC, Princeton, NJ
Joerg Henkel - NEC, Princeton, NJ
Venkata Jakkula - NEC, Princeton, NJ